Conventionally, MOS image sensors have been used in imaging applications, such as still photography and video imaging products. One reason for the utilization of MOS image sensors in these applications is the MOS image sensors' compatibility with VLSI circuit design and fabrication processing.
Since low-cost, large-scale MOS design and fabrication technologies that have been developed for large-volume VLSI circuits can be directly employed in the production of MOS imaging arrays, MOS imaging arrays are, in general, much more cost effective than imaging arrays produced based on CCD technologies. As a result, for many applications, and particularly for consumer products, a MOS imaging array is preferred over a corresponding CCD imaging array.
Another factor in utilizing MOS imaging arrays over CCD technology imaging arrays is their ability to operate at high speeds and low powers. Typically, power consumption of MOS imagers is dominated by amplifiers used in correlated double sampling (CDS) circuits and A/D converters. Therefore, in a low power MOS imaging array, it is critical to provide amplifiers that can properly operate at the lower power restraints.
One possible solution to the power constraints of a low power high speed MOS imaging array is the utilization of a conventional operational transconductance amplifier in the analog signal processing circuits.
A conventional operational transconductance amplifier circuit is depicted in FIG. 4. Although a fully-differential version of an operational transconductance amplifier circuit is shown, implementation of a single-ended version is straightforward. For the simplicity of illustration, a common-mode feedback circuit that is often required in a fully-differential amplifier is omitted.
M1 and M2 comprise the input differential pair. A cascode current source provided by M13 and M14 serves as a tail current source for a differential input stage consisting of M1, M2, M3, and M4. An input voltage is applied differentially at nodes labeled VINP and VINN. Differential outputs are obtained at nodes labeled VOUTP and VOUTN.
The currents through the input transistors M1 and M2 are mirrored by a first current mirror, M3 and M5, and a second current mirror, M4 and M6, respectively. The mirrored currents go through cascode stages M7 and M8 and show up at the output nodes VOUTP and VOUTN.
The cascode stages are employed in order to increase the output resistance. The cascode current sources with high output resistance, provided by M9, M10, M11, and M12, complete the output stage.
IBIAS and M15 set up the gate voltages for M11, M12, and M14 fixing their currents. Nominally, the width of M14 is twice the width of M11 or M12.
It can be shown that this arrangement makes the nominal drain currents of M1 and M2 equal to those of M11 and M12, a necessary condition for both the input and the output stages to have the same bias current level.
Although a conventional operational transconductance amplifier, as illustrated in FIG. 4, may meet the power constraints mentioned above, it is also well known that the current mirror gain factor of the operational transconductance amplifier typically increases the noise level in the output signal of an operational transconductance amplifier. Substantial noise increase is undesirable in a MOS imaging system because the quality of images from the MOS imaging array is highly sensitive to noise.
Therefore, it is desirable to provide analog signal processing circuits that operate effectively under the low power conditions. Moreover, it is desirable to provide amplification in the analog signal processing circuitry without introducing substantial increase in noise that would detrimentally affect the quality of images from the MOS imaging array. Furthermore, it is desirable to provide an amplifier that has the low power characteristics without introducing substantial increase of noise into the MOS imaging array signal.